what r transaction synchronistion
bugs

Question Posted / guest

Synchronization in DSVM (distributed shared virtual memory)
process level instead of only at the memory access level.
idea in the context of transaction synchronization,
devising two-phase locking-based algorithms under two DSVM
with and without an underlying memory coherence system.
They compare the performances of the two algorithms and
argue that significant performance gain can potentially
result from bypassing memory coherence and supporting
process synchronization directly on distributed memory.
They also study the role of the optimistic algorithms in
transaction synchronization in DSVM.
Synchronization bugs are caused by physical phenomena which
cause the actual behavior of a chip to be different than
predicted according to the functional model. Traditionally,
verification methods such as dynamic simulation and model
checking use a synchronous model, whereas the actual
behavior is according to an asynchronous model. Because of
this, synchronization bugs are very hard to trace. Using a
model checker we were able to create a model closer to the
actual behavior, and retrace many synchronization bugs.
Because model checking allows us to introduce non-
determinism when checking a VLSI design, and because of its
ability to produce counter examples for specifications that
fail, we find that model checking is the ideal tool for
reproducing synchronization bugs.