Tell me about some of your hobby projects that you've written in your off time.
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Explain the characteristics of embedded system?
What are the differences between stateless and stateful systems, and impacts of state on parallelism.
Explain me what is endianness of a system and how do different systems communicate with each other?
This program is in verilog and need help to get it working correctly. This is the code i have so far. Please help. Simple testbench would be great. Thanks\ 'define vend_a_drink {D,dispense,collect} = {IDLE,2'b11}; module drink_machine(nickel_in, dime_in, quarter_in, collect, nickel_out, dime_out, dispense, reset, clk) ; parameter IDLE=0,FIVE=1,TEN=2,TWENTY_FIVE=3, FIFTEEN=4,THIRTY=5,TWENTY=6,OWE_DIME=7; input nickel_in, dime_in, quarter_in, reset, clk; output collect, nickel_out, dime_out, dispense; reg collect, nickel_out, dime_out, dispense; reg [2:0] D, Q; /* state */ // synopsys state_vector Q always @ ( nickel_in or dime_in or quarter_in or reset ) begin nickel_out = 0; dime_out = 0; dispense = 0; collect = 0; if ( reset ) D = IDLE; else begin D = Q; case ( Q ) IDLE: if (nickel_in) D = FIVE; else if (dime_in) D = TEN; else if (quarter_in) D = TWENTY_FIVE; FIVE: if(nickel_in) D = TEN; else if (dime_in) D = FIFTEEN; else if (quarter_in) D = THIRTY; TEN: if (nickel_in) D = FIFTEEN; else if (dime_in) D = TWENTY; else if (quarter_in) 'vend_a_drink; TWENTY_FIVE: if( nickel_in) D = THIRTY; else if (dime_in) 'vend_a_drink; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; dime_out = 1; end FIFTEEN: if (nickel_in) D = TWENTY; else if (dime_in) D = TWENTY_FIVE; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; end THIRTY: if (nickel_in) 'vend_a_drink; else if (dime_in) begin 'vend_a_drink; nickel_out = 1; end else if (quarter_in) begin 'vend_a_drink; dime_out = 1; D = OWE_DIME; end TWENTY: if (nickel_in) D = TWENTY_FIVE; else if (dime_in) D = THIRTY; else if (quarter_in) begin 'vend_a_drink; dime_out = 1; end OWE_DIME: begin dime_out = 1; D = IDLE; end endcase end end always @ (posedge clk ) begin Q = D; end endmodule
Explain the difference between testing and verification?
What is the need for having multibyte data input and output buffers in case of device ports?
Name three primary attributes of object-oriented design. Describe what they mean and why they're important.
Explain me what are the different types of system involved in embedded system?
Describe a time when you collaborated with designers and engineers to deploy a new product. What was your role?
What's the difference between locking and lockless (optimistic and pessimistic) concurrency models?
Why does pre-emptive multi-threading used to solve the central controller problem?
How does inversion of control relate to dependency injection?