Design any FSM in VHDL or Verilog?

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Design any FSM in VHDL or Verilog?..

Answer / rahul singhal

-----By RAHUL SINGHAL----
----This is the code of a FSM that implements a toll booth -
----controller

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of
specific package---

ENTITY tollbooth2 IS
PORT (Clock,car_s,RE : IN STD_LOGIC;
coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
r_light,g_light,alarm : OUT STD_LOGIC);
END tollbooth2;

ARCHITECTURE Behav OF tollbooth2 IS
TYPE state_type IS
(NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE
D);
------GOTZERO = PAID $0.00---------
------GOTFIV = PAID $0.05----------
------GOTTEN = PAID $0.10----------
------GOTFIF = PAID $0.15----------
------GOTTWEN = PAID $0.20---------
SIGNAL present_state,next_state : state_type;

BEGIN
-----Next state is identified using present state,car &
coin sensors------
PROCESS(present_state,car_s,coin_s)
BEGIN

CASE present_state IS
WHEN NO_CAR =>
IF (car_s = '1') THEN
next_state <= GOTZERO;
ELSE
next_state <= NO_CAR;
END IF;

WHEN GOTZERO =>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s = "00") THEN
next_state <= GOTZERO;
ELSIF (coin_s = "01") THEN
next_state <= GOTFIV;
ELSIF (coin_s ="10") THEN
next_state <= GOTTEN;
END IF;

WHEN GOTFIV=>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s = "00") THEN
next_state <= GOTFIV;

ELSIF (coin_s = "01") THEN
next_state <= GOTTEN;
ELSIF (coin_s <= "10") THEN
next_state <= GOTFIV;
END IF;

WHEN GOTTEN =>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s ="00") THEN
next_state <= GOTTEN;

ELSIF (coin_s="01") THEN
next_state <= GOTFIV;
ELSIF (coin_s="10") THEN
next_state <= GOTTWEN;
END IF;

WHEN GOTFIF =>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s = "00") THEN
next_state <= GOTFIF;

ELSIF (coin_s ="01") THEN
next_state <= GOTTWEN;
ELSIF (coin_s = "10") THEN
next_state <= GOTTWEN;
END IF;

WHEN GOTTWEN =>
next_state <= CAR_PAID;

WHEN CAR_PAID =>
IF (car_s = '0') THEN
next_state <= NO_CAR;
ELSE
next_state<= CAR_PAID;
END IF;

WHEN CHEATED =>
IF (car_s = '1') THEN
next_state <= GOTZERO;
ELSE
next_state <= CHEATED;
END IF;

END CASE;
END PROCESS;-----End of Process 1
-------PROCESS 2 for STATE REGISTER CLOCKING--------
PROCESS(Clock,RE)
BEGIN
IF RE = '1' THEN
present_state <= GOTZERO;
----When the clock changes from low to high,the state of
the system
----stored in next_state becomes the present state-----
ELSIF Clock'EVENT AND Clock ='1' THEN
present_state <= next_state;
END IF;
END PROCESS;-----End of Process 2-------
---------------------------------------------------------
-----Conditional signal assignment statements----------
r_light <= '0' WHEN present_state = CAR_PAID ELSE '1';
g_light <= '1' WHEN present_state = CAR_PAID ELSE '0';
alarm <= '1' WHEN present_state = CHEATED ELSE '0';
END Behav;

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Design any FSM in VHDL or Verilog?..

Answer / arpan

// Tollbooth controller with VERILOG. My design contains 4
//inputs and one output. Output is : 1. stop_go signal ->
//This signal contains two leds i.e. green and red. Green
//denotes vehicle can go and Red denotes vehicle to stop.
//Input is 1.x -> This signal denotes presence of vehicle
//in toll booth. 2.heavy_light_vehicle -> This signal
//denotes weather its a heavy vehicle or light vehicle and
//pay accordingly. For heavy vehicle pay Rs 5 for light
//vehicle pay Rs 1. 3.Other input signal is clk and clear.

module controller (stop_go,X,heavy_light_vehicle,clk,clear);

input x, clk, clear, heavy_light_vehicle;

output stop_go;

reg stop_go;

reg [2:0]pay; //Amt that is being paid.

reg [0:1] state, next_state;

parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;

parameter red = 1'b0, green = 1'b1;

always @ (posedge clk)

begin

if (clear)
begin
stop_go <= red;
state <= s0;
pay <= 1'd0;
end
else
state <= next_state;
end

always @ (state or X or pay)

begin

case (state)

s0 : if (X)
next_state = s1;
else
next_state = s0;
pay = 3'd0;

s1 : if (heavy_light_vehicle)
begin
pay = 3'd1;
next_state = s2;
end
else
begin
pay = 3'd5;
next_state = s2;
end

s2 : if (pay == 3'd1 || pay == 3'd5)
begin
stop_go = green;
next_state = s3;
else
next_state = s1; // If correct amount is
//not paid then next_state again goes to s1

s3 : begin
stop_go = red;
next_state = s0;
end

default : next_state = s0;
endcase

end

endmodule

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