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Design any FSM in VHDL or Verilog?

Answer Posted / arpan

// Tollbooth controller with VERILOG. My design contains 4
//inputs and one output. Output is : 1. stop_go signal ->
//This signal contains two leds i.e. green and red. Green
//denotes vehicle can go and Red denotes vehicle to stop.
//Input is 1.x -> This signal denotes presence of vehicle
//in toll booth. 2.heavy_light_vehicle -> This signal
//denotes weather its a heavy vehicle or light vehicle and
//pay accordingly. For heavy vehicle pay Rs 5 for light
//vehicle pay Rs 1. 3.Other input signal is clk and clear.

module controller (stop_go,X,heavy_light_vehicle,clk,clear);

input x, clk, clear, heavy_light_vehicle;

output stop_go;

reg stop_go;

reg [2:0]pay; //Amt that is being paid.

reg [0:1] state, next_state;

parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;

parameter red = 1'b0, green = 1'b1;

always @ (posedge clk)

begin

if (clear)
begin
stop_go <= red;
state <= s0;
pay <= 1'd0;
end
else
state <= next_state;
end

always @ (state or X or pay)

begin

case (state)

s0 : if (X)
next_state = s1;
else
next_state = s0;
pay = 3'd0;

s1 : if (heavy_light_vehicle)
begin
pay = 3'd1;
next_state = s2;
end
else
begin
pay = 3'd5;
next_state = s2;
end

s2 : if (pay == 3'd1 || pay == 3'd5)
begin
stop_go = green;
next_state = s3;
else
next_state = s1; // If correct amount is
//not paid then next_state again goes to s1

s3 : begin
stop_go = red;
next_state = s0;
end

default : next_state = s0;
endcase

end

endmodule

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