Answer / hari

Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous input signals to the flip-flop

Refer the following image inorder to visualize hold time

https://en.wikipedia.org/wiki/File:FF_Tsetup_Thold_Toutput.svg

Answer / reshma

the time at which the input signal is steady

give some important questions in Airport Authority of india junior Engineer ATC exam?

0 Answers  

---

WAT EXACTLY DOES IT DO

0 Answers  

---

Why value of rx level is always negative?

0 Answers   Ericsson,

---

what is the effect of increase resistance on reluctance?

0 Answers  

---

AT WHICH VOLTAGE AN OP-AMP OPERATE

11 Answers   TCS, TSC,

---

---

Explain what is a voltage follower?

0 Answers  

---

What are the two types of control strategies?

0 Answers  

---

how a log ratio amplifier works?

0 Answers  

---

what should I refer for examination of BSNL-TTA. Please suggest me good reference...so that I can clear this exam.

0 Answers  

---

Why we need biasing for transistor, fet and mosfet?

0 Answers  

---

why ic 741 is different 4 m other ic's and y these ic 741 is used in integrated circuits?

1 Answers  

---

what is electronics?

10 Answers   Bhel,

---