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86 Family (470) - VLSI (297)
- DSP (55)
- Embedded Systems AllOther (399)
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
1087Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
1093Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1593You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1507What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1248How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1175For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1229Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1411Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1244
What is the bus in a microcontroller?
Explain interrupt latency and how can we decrease it?
Express the discrete time signal x(n) as a summation of impulses.
How many interrupts are there in 8085?
What is the use of having the const qualifier?
how does the 8086 differ from the 8085 microprocessor?
What transistor level design tools are you proficient with? What types of designs were they used on?
Tell me how does input/output bus functions?
What is the need for dmac in es?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Why do we need virtual device drivers when we have physical device drivers?
what is dsp?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
How is EPROM generally erased
What was your role in the silicon evaluation/product ramp? What tools did you use?
