Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
685Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1064You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
952What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
762For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
707Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
843Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
814For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
938Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
782Post New Infosys VLSI Interview Questions
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