Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
1146Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
1158Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
1087Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
1093Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1593You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1507What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1248How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1175For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1229Post New Infosys Interview Questions
What is a hive in big data?
How to get the type of arguments passed to a function?
What is a partitioned view?
Why you want to join NABARD?
How xslt works with xml?
Which dialog box allows users to switch to another area of the application?
Why do we need servlets and jsp?
What is hibernate database?
Please tell me some products/services of Capital One.
How to list all indexes in your schema?
How do I open applicationhost config?
Distinguish between splunk apps and add-ons?
How does reference counting manage memory allocated objects?
What is ctrl f8?
What is basic authentication in web api?