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What are set up time & hold time constraints What do they
signify Which one is critical for estimating maximum clock
frequency of a circuit?
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Answer Posted / vinita jain
Set up time constraint signifies how late the input signal
can arrive before the active edge of the flip-flop. Smaller
the set up time, the better.
Hold time on the other hand signifies how long the value at
the input needs to be held stable after the the active edge.
Again the smaller the hold time, the better.
For estimating maximum clock frequency, set up time is critical.
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