Design a circuit to detect when 3 and only 3 bits are set
out of 8 bits.(eg. o0101100)
Answer Posted / gautam
I have modified it a bit,
MOVL XAR1, #Data
MOVL XAR0, #0x00
MOVL XAR2, #0x00
Loop:
TBIT *XAR1,#XAR2
BF Loop1, NTC
INR AR0
Loop1:
INR AR2
MOV AL, *XAR0
CMP AL, @0x03
BF Action, EQ
MOV AL, *XAR2
CMP AL, @0x08
BF Loop, NEQ
Loop3:
EXIT
Action:
Is This Answer Correct ? | 0 Yes | 5 No |
Post New Answer View All Answers
Tell me why do we need virtual device drivers when we have physical device drivers?
How can to check the working of a sensor deployed in a project?
What is the difference between a web server, web farm and web garden? How would your web application need to change for each?
Explain me what is kernel paging?
What is a memory leak? What is a segmentation fault?
What is so great about
Why embedded system is useful?
What are the essential components of embedded system?
What is the use of having the const qualifier?
What are the differences between analytical and computational modeling?
This program is in verilog and need help to get it working correctly. This is the code i have so far. Please help. Simple testbench would be great. Thanks\ 'define vend_a_drink {D,dispense,collect} = {IDLE,2'b11}; module drink_machine(nickel_in, dime_in, quarter_in, collect, nickel_out, dime_out, dispense, reset, clk) ; parameter IDLE=0,FIVE=1,TEN=2,TWENTY_FIVE=3, FIFTEEN=4,THIRTY=5,TWENTY=6,OWE_DIME=7; input nickel_in, dime_in, quarter_in, reset, clk; output collect, nickel_out, dime_out, dispense; reg collect, nickel_out, dime_out, dispense; reg [2:0] D, Q; /* state */ // synopsys state_vector Q always @ ( nickel_in or dime_in or quarter_in or reset ) begin nickel_out = 0; dime_out = 0; dispense = 0; collect = 0; if ( reset ) D = IDLE; else begin D = Q; case ( Q ) IDLE: if (nickel_in) D = FIVE; else if (dime_in) D = TEN; else if (quarter_in) D = TWENTY_FIVE; FIVE: if(nickel_in) D = TEN; else if (dime_in) D = FIFTEEN; else if (quarter_in) D = THIRTY; TEN: if (nickel_in) D = FIFTEEN; else if (dime_in) D = TWENTY; else if (quarter_in) 'vend_a_drink; TWENTY_FIVE: if( nickel_in) D = THIRTY; else if (dime_in) 'vend_a_drink; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; dime_out = 1; end FIFTEEN: if (nickel_in) D = TWENTY; else if (dime_in) D = TWENTY_FIVE; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; end THIRTY: if (nickel_in) 'vend_a_drink; else if (dime_in) begin 'vend_a_drink; nickel_out = 1; end else if (quarter_in) begin 'vend_a_drink; dime_out = 1; D = OWE_DIME; end TWENTY: if (nickel_in) D = TWENTY_FIVE; else if (dime_in) D = THIRTY; else if (quarter_in) begin 'vend_a_drink; dime_out = 1; end OWE_DIME: begin dime_out = 1; D = IDLE; end endcase end end always @ (posedge clk ) begin Q = D; end endmodule
Explain the concept of separation of concerns?
What are the advantages and disadvantages of separation of concerns?
What are little endian and big endian types of storage? How can you identify which type of allocation a system follows?
Describe a software development life cycle that you've managed.