Interested to Buy Any Domain ? << Click Here >> for more details...
Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ?
- 4 Answers
- 13902 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / mallikarjun patil
I have worked on design consit of 5 stage pipeline
processor.
With 5 stage pipeline it takes minimum 5 clock cycle to to
execute a instuction. So latency of instuction is5 clock
cycles.
Through put is one instruction per clock cycle + initial
overhed of 4 clock cycle
| Is This Answer Correct ? | 27 Yes | 3 No |
Post New Answer View All Answers
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
What is the critical path in a SRAM?
Explain sizing of the inverter?
Explain how Verilog is different to normal programming language?
What was your role in the silicon evaluation or product ramp? What tools did you use?
what is Slack?
How binary number can give a signal or convert into a digital signal?
What is the purpose of having depletion mode device?
Give the cross-sectional diagram of the cmos.
what is multiplexer?
What happens if we delay the enabling of Clock signal?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What is the difference between nmos and pmos technologies?
What are the steps involved in preventing the metastability?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
