Answer Posted / chandu
LVS -LAYOUT VERSUS SHEMATIC TEST WHICH COMES IN THE
STRACTURIAL DOMAIN IN WHICH WE WILL FIRST SHEMATIC THE
CIRCUT AND AFTER BY USING TOOLS WE WILL MAKE THE LAYOUT BY
COMAPARING THE BOTH THINGS JUST FOR SEEING WHEATHER ANY
MISTAKES IS THERE OR NOT ...........IT IS TESTING PROCESS
DRC-DESIGN RULE CHECK THESE USEDE TESTING THE LAYOUT DESIGN
AND FOR CHECKING THE CIRCUIT
Is This Answer Correct ? | 9 Yes | 15 No |
Post New Answer View All Answers
Explain Cross section of a PMOS transistor?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Draw the Layout of an Inverter?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is the ideal input and output resistance of a current source?
What are the different ways in which antenna violation can be prevented?
What are the different measures that are required to achieve the design for better yield?
What types of CMOS memories have you designed? What were their size? Speed?
Explain how MOSFET works?
What happens if we delay the enabling of Clock signal?
Implement a 2 I/P and gate using Tran gates?
What are the Advantages and disadvantages of Mealy and Moore?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Explain what is scr (silicon controlled rectifier)?