Answer Posted / daud
when the Vds becomes greater than Vgs-Vt, the channel near drains becomes depleted and effective channel length reduces. This in effect reduces the resistance of channel as the drain voltage increases. This effect is called channel length modulation
Is This Answer Correct ? | 1 Yes | 0 No |
Post New Answer View All Answers
Draw the SRAM Write Circuitry
Draw the Layout of an Inverter?
Explain Basic Stuff related to Perl?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What is the function of chain reordering?
Draw a 6-T SRAM Cell and explain the Read and Write operations
what is the difference between the TTL chips and CMOS chips?
What is the difference between nmos and pmos technologies?
Explain the Various steps in Synthesis?
How can you model a SRAM at RTL Level?
What are the different ways in which antenna violation can be prevented?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
What are the different design constraints occur in the synthesis phase?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?