what is the difference between the testing and verification?
Answer Posted / wilszz
testing is performed on a silicon level after the design is made by foundry. it is chariterization test. However verification is done before tapeout and during the design stage, it mainly has netlist- verification and layout verification
Is This Answer Correct ? | 3 Yes | 0 No |
Post New Answer View All Answers
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Design an 8 is to 3 encoder using 4 is to encoder?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Explain depletion region.
why is the number of gate inputs to CMOS gates usually limited to four?
Are you familiar with the term MESI?
What is the function of chain reordering?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What are the steps involved in designing an optimal pad ring?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Explain the Charge Sharing problem while sampling data from a Bus?
What is the critical path in a SRAM?