what is the difference between the testing and verification?

Answer Posted / wilszz

testing is performed on a silicon level after the design is made by foundry. it is chariterization test. However verification is done before tapeout and during the design stage, it mainly has netlist- verification and layout verification 

Is This Answer Correct ?    3 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1045


Design an 8 is to 3 encoder using 4 is to encoder?

960


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

840


Explain depletion region.

708


why is the number of gate inputs to CMOS gates usually limited to four?

907






Are you familiar with the term MESI?

2246


What is the function of chain reordering?

708


Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3376


What are the steps involved in designing an optimal pad ring?

803


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1131


In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

797


What happens if we use an Inverter instead of the Differential Sense Amplifier?

2579


What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2101


Explain the Charge Sharing problem while sampling data from a Bus?

2223


What is the critical path in a SRAM?

2733