Answer Posted / kantha
LVS- LAYOUT VERSUS SHEMATIC TEST FROM NETLIST DESIGN
(NORMALLY MANUAL METHOD)
DRC-DESIGN RULE CHECK(EX SPICE TOOL WILL GENERATE ERRORS IF
YOUR DESIGN NOT MET THE STANDARD DESIGN RULES)
Is This Answer Correct ? | 9 Yes | 16 No |
Post New Answer View All Answers
Explain about 6-T XOR gate?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
What is threshold voltage?
what is the difference between the TTL chips and CMOS chips?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
How does Vbe and Ic change with temperature?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
What is the purpose of having depletion mode device?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Explain how logical gates are controlled by Boolean logic?
Explain Basic Stuff related to Perl?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?