Answer Posted / anuj kumar

The n-channel device requires +ve Vgs and the p-channel device requires negative Vgs

What products have you designed which have entered high volume production?

2388

---

What's the price in 1K quantity?

2778

---

Give the cross-sectional diagram of the cmos.

942

---

Explain about 6-T XOR gate?

1177

---

What are the Factors affecting Power Consumption on a chip?

1226

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1397

---

Explain the Charge Sharing problem while sampling data from a Bus?

4654

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1538

---

For CMOS logic, give the various techniques you know to minimize power consumption

1346

---

Why does the present vlsi circuits use mosfets instead of bjts?

1223

---

How can you construct both PMOS and NMOS on a single substrate?

4930

---

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1309

---

Explain the working of 4-bit Up/down Counter?

4392

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1055

---

Draw the stick diagram of a NOR gate. Optimize it

1225

---