Answer Posted / seokchai

latch does not have clock while flip-flop does

Cross section of a PMOS transistor?

4773

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Explain the Working of a 2-stage OPAMP?

1198

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How about voltage source?

2272

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What are the different design techniques required to create a layout for digital circuits?

1043

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3267

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1608

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What is the ideal input and output resistance of a current source?

3015

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Write a VLSI program that implements a toll booth controller?

3988

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What types of CMOS memories have you designed? What were their size? Speed?

4662

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Explain Cross section of an NMOS transistor?

1039

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1573

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Are you familiar with the term MESI?

2744

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What was your role in the silicon evaluation or product ramp? What tools did you use?

2328

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

1156

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What are the Factors affecting Power Consumption on a chip?

1286

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