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Answer Posted / ketan
yes the above answer is true and this condition arises as the time period of the flip flop clock is less than the time period of input clock. so as long as the input clock stays high output of flip flop will keep changing.
this can be avoided by using master slave flip flop in which two jk flip flop are connected but each is provided complementary clock pulse i.e. if master has high clock pulse than slave will be having low clock pulse. so till the clock pulse of master flip flop is high then slave clock pulse will be low, and it's output will not change and when slave has high clock pulse then output will change and in that case master will be inactive as it's clock pulse will be low.
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