What?s the difference between Testing & Verification?

Answer Posted / john

Testing is the process of identifying defects in a product.
Verification is the process of ensuring that the product
complies with its specification. Validation is the process
of ensuring that the product meets the users' needs.
Although linked, these are obviously separate. A product may
be defect free but not what was specified or needed; it may
have defects and be not as specified, but may still meet
user need; it may meet specification, but have defects and
not meet the users' need (probably the most common outcome
of software projects!).

Is This Answer Correct ?    30 Yes 2 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Draw the SRAM Write Circuitry

780


Explain what is the use of defpararm?

755


Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2445


What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2101


If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

2125






Mention what are the two types of procedural blocks in Verilog?

865


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2446


What happens if we delay the enabling of Clock signal?

1888


Draw the stick diagram of a NOR gate. Optimize it

887


Explain what is scr (silicon controlled rectifier)?

718


What happens if we use an Inverter instead of the Differential Sense Amplifier?

2581


For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2003


what is verilog?

715


In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

799


Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

783