Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / dyamanna.siddappa
LVS mean's layout versus schmetic.. compare to layout and
schmetic..
DRC mean's design rule check.. layer to layer between
distence in vlsi layout design
| Is This Answer Correct ? | 8 Yes | 4 No |
Post New Answer View All Answers
What is the function of enhancement mode transistor?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
What are the Factors affecting Power Consumption on a chip?
What is the ideal input and output resistance of a current source?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Working of a 2-stage OPAMP?
How does Vbe and Ic change with temperature?
What transistor level design tools are you proficient with? What types of designs were they used on?
Explain various adders and difference between them?
What are the different ways in which antenna violation can be prevented?
Explain depletion region.
What is the difference between nmos and pmos technologies?
Explain what is Verilog?
What is Body Effect?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
