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how 2 design a mod 6 synchronous counter using jk flip flop?
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Answer Posted / aniket
binary for 6 is 110..we will need 3 MS JK FF i.e. using ic
7476....we need to design a truth table for that...
till state 0 to 5(6 states) put your o/p as 1...ie.e those
are valid states and for the remaining ones those are the
invalid states....then draw k-map and design the
combinational logic....put all ur preset and J0 K0..i/ps of
FF to logic 1 and accordingly clock the FF
and put the o/p of the combinaional logic to the clear of
thr ff......in order to clear the states after 5th.....
hope this was usefull....
| Is This Answer Correct ? | 33 Yes | 8 No |
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