Answer Posted / mekuria

That is also my question.

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2785

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What does the above code synthesize to?

2518

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1407

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What is the difference between cmos and bipolar technologies?

1087

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

3263

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What does it mean “the channel is pinched off”?

1301

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What is the critical path in a SRAM?

3104

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1169

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1397

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1586

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1154

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Tell me how MOSFET works.

2367

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Give the cross-sectional diagram of the cmos.

942

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1221

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What is the difference between nmos and pmos technologies?

1059

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