Interested to Buy Any Domain ? << Click Here >> for more details...
WHAT IS THE DIFFERENCE B/W VERILOG AND VHDL
- 2 Answers
- 12637 Views
- Infosys, TCS, I also Faced
- E-Mail Answers
Answer Posted / refedo
1. Verilog is based on C, while VHDL is based on Pascal and Ada.
2. Unlike Verilog, VHDL is strongly typed.
3. Ulike VHDL, Verilog is case sensitive.
4. Verilog is easier to learn compared to VHDL.
5. Verilog has very simple data types, while VHDL allows
users to create more complex data types.
6. Verilog lacks the library management, like that of VHDL.
Read more: Difference Between Verilog and VHDL | Difference
Between
http://www.differencebetween.net/technology/difference-between-verilog-and-vhdl/#ixzz0ti9ocWih
| Is This Answer Correct ? | 20 Yes | 3 No |
Post New Answer View All Answers
What is DRX? Why do we need it?
Wats da diff b/w ithernet communication and profibus communication?
what are the basic courses can be done for ece branch?
What are active & passive elements in BTS?
In connections of mcb, is it necessary that the incoming side supply should be connected at top side of mcb. Whether this has any effect in tripping of mcb in case of fault?
What do you mean by donor and acceptor impurities?
Can you help me correct FM transmitter circuit?
Hai Frds, i want to join in testing tools course, pls sugest good institute. And pls tel about Mind Q institute & phone num of Nareswar Roa sir plss, ple mail me plssssss
what are the applications of integrators?
State faraday`s law of induction.
What are the advantages of scr and triac?
can i get the 2007-2009 question papers of APGENCO? plzzzzzz
Give the expression for the vco free running frequency.
Tell me why gold is added to the p-n junction?
Explain what are the advantages of using a voltage follower amplifier?
