Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ?
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Answer Posted / kiran chowdary
Throughput is 1 instruction/clock cycle. It is a dumb answer to say the latency as 5 cycles. It is pipelined architecture. Only during initial time it takes 5 cycles to fetch and all that. Later on all executions are pipelined so it takes only 1 cycle to execute one instruction unless there is any blocking activity like memory write back etc.
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