Answer Posted / shikha chauhan

The condition S=R=1 is not allowed in SR flip-flop, this is
eliminated by JK flip flop by using feedback connection
from output to input of gate 1 and 2 because of the
feedback connection Q(Q')at the i/p to K(J). The i/p will
change during clk pulse CP=1, if the o/p changes the state.

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