Answer Posted / kazem

I want 300 page for information noise in MOSFET and CMOS ?
tank you very mach.

Explain the working of Insights of a pass gate ?

1308

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What types of high speed CMOS circuits have you designed?

2616

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Explain how Verilog is different to normal programming language?

1374

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What is the function of tie-high and tie-low cells?

1150

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What are the ways to Optimize the Performance of a Difference Amplifier?

2506

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Explain how binary number can give a signal or convert into a digital signal?

1167

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3930

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Explain the three regions of operation of a mosfet.

1147

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1651

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Explain what is the depletion region?

1137

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Differences between Array and Booth Multipliers?

4144

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Describe the various effects of scaling?

4841

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Draw a CMOS Inverter. Explain its transfer characteristics

1232

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Explain the operation considering a two processor computer system with a cache for each processor.

2896

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1242

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