Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What is FPGA?

Answer Posted / shravan

FPGA is Field programmable gate array.
A field programmable gate array (FPGA) is an integrated
circuit (IC) that includes a two-dimensional array of
general-purpose logic circuits, called cells or logic
blocks, whose functions are programmable.
An FPGA is similar to a PLD, but whereas PLDs are generally
limited to hundreds of gates, FPGAs support thousands of gates.

Is This Answer Correct ?    8 Yes 2 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Basic Stuff related to Perl?

2823


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2891


Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1116


Explain about 6-T XOR gate?

1283


How do you size NMOS and PMOS transistors to increase the threshold voltage?

3035


What is Noise Margin? Explain the procedure to determine Noise Margin?

2462


Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

3145


What are the changes that are provided to meet design power targets?

1122


How about voltage source?

2272


Explain the operation considering a two processor computer system with a cache for each processor.

2852


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1608


What is the difference between synchronous and asynchronous reset?

1094


What are the main issues associated with multiprocessor caches and how might you solve them?

2237


Design an 8 is to 3 encoder using 4 is to encoder?

1333


Explain what is Verilog?

1115