Answer Posted / guest

PS I/P NS O/P
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S3 0
S2 1 S1 0
S3 0 S0 0
S3 1 S1 1


when s2=1 it should go to s1... otherwise it will not detect
the sequence like "...11101..."

Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1012

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2390

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4060

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Explain what is slack?

1014

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2834

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What is the difference between nmos and pmos technologies?

1059

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1503

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1221

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What types of CMOS memories have you designed? What were their size? Speed?

3086

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

2967

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Explain what is scr (silicon controlled rectifier)?

1017

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

1089

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

1092

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Cross section of a PMOS transistor?

4720

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1397

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