Interested to Buy Any Domain ? << Click Here >> for more details...
How do you detect a sequence of "1101" arriving serially
from a signal line?
- 7 Answers
- 20056 Views
- nvidia, I also Faced
- E-Mail Answers
Answer Posted / govind vijayakumar
Just put a SIPO (Serial In Paralle Out)Network at the
output, followed by a gate network.
4 parallel outputs from the SIPO are taken and the signal
lines whose output is supposed to be one are fed to a 3
input and gate. The 0 output is fed to a not gate and the
output of both the gates are anded together. If this
sequence comes then output will be one, otherwise 0.
| Is This Answer Correct ? | 5 Yes | 5 No |
Post New Answer View All Answers
Explain how Verilog is different to normal programming language?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
what is SCR (Silicon Controlled Rectifier)?
Implement a 2 I/P and gate using Tran gates?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What types of CMOS memories have you designed? What were their size? Speed?
Explain what is scr (silicon controlled rectifier)?
Tell me how MOSFET works.
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
Explain the Various steps in Synthesis?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is the difference between the mealy and moore state machine?
Explain what is the depletion region?
Explain what is the use of defpararm?
What happens if we delay the enabling of Clock signal?
