Answer Posted / jelydonut
LVS is when the netlist (normally synthesized verilog) and
the physical layout (gdsii) match connections (ie cells and
wire connections match the physical layout).
DRC is when the physical layout is checked to make sure that
the layout of the part is manufacturable using the process
that the foundry is capable of. (ie if two metal wires are
too close together on the same layer, they may short during
the manufacturing process, affecting yield, just one of many
possible examples on this one)
Some of the other answers are right, but don't explain it well.
| Is This Answer Correct ? | 48 Yes | 6 No |
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