Interested to Buy Any Domain ? << Click Here >> for more details...
Describe a finite state machine that will detect three
consecutive coin tosses (of one coin) that results in heads.
- 1 Answers
- 18243 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / amar
State machine to detect 3 consecutive heads appearing in
multiple tosses;
state 1 : initial state
As long as the toss results in TAIL , in this state
If the toss results in HEAD go to state 2
state 2 : HEAD1 resulted
in the next toss , If TAIL is resulted go to
the initial state1 . If HEAD is resulted go to
state3.
state3 : HEAD2 is resulted
in the next toss , If TAIL is resulted go to
the initial state1 . If HEAD is resulted go to
state4.
state4 : HEAD3 is resulted and this is the final state
As long as the HEAD results in each next toss
be in state 4. If any toss results in TAIL go to
initial state1
| Is This Answer Correct ? | 77 Yes | 3 No |
Post New Answer View All Answers
Draw a CMOS Inverter. Explain its transfer characteristics
Insights of a 4bit adder/Sub Circuit?
What is the critical path in a SRAM?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
What does it mean “the channel is pinched off”?
what is multiplexer?
What is look up table in vlsi?
What is the difference between the mealy and moore state machine?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Explain Basic Stuff related to Perl?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Are you familiar with the term MESI?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Explain the Various steps in Synthesis?
Draw the Layout of an Inverter?
