Describe a finite state machine that will detect three
consecutive coin tosses (of one coin) that results in heads.

Answer Posted / amar

State machine to detect 3 consecutive heads appearing in
multiple tosses;

state 1 : initial state
As long as the toss results in TAIL , in this state
If the toss results in HEAD go to state 2
state 2 : HEAD1 resulted
in the next toss , If TAIL is resulted go to
the initial state1 . If HEAD is resulted go to
state3.
state3 : HEAD2 is resulted
in the next toss , If TAIL is resulted go to
the initial state1 . If HEAD is resulted go to
state4.
state4 : HEAD3 is resulted and this is the final state
As long as the HEAD results in each next toss
be in state 4. If any toss results in TAIL go to
initial state1

Is This Answer Correct ?    75 Yes 3 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Draw the stick diagram of a NOR gate. Optimize it

770


Explain what is scr (silicon controlled rectifier)?

627


For CMOS logic, give the various techniques you know to minimize power consumption

873


How to improve these parameters? (Cascode topology, use long channel transistors)

1718


Draw a 6-T SRAM Cell and explain the Read and Write operations

809






How about voltage source?

1843


Insights of a 4bit adder/Sub Circuit?

2860


Explain Cross section of a PMOS transistor?

759


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1068


what is Slack?

715


What are the Factors affecting Power Consumption on a chip?

778


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

736


What was your role in the silicon evaluation or product ramp? What tools did you use?

1869


Explain the three regions of operation of a mosfet.

638


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3398