Answer Posted / lu

Charge sharing is an undesirable signal integrity phenomenon
observed most commonly in the domino logic family of digital
circuits. The charge sharing problem occurs when the charge
which is stored at the output node in the phase is shared
among the output or junction capacitance of transistors
which are in the evaluation phase. Charge sharing may
degrade the output voltage level or even cause erroneous
output value

How does Vbe and Ic change with temperature?

3518

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1081

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What is the function of tie-high and tie-low cells?

1089

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1209

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What is the purpose of having depletion mode device?

1056

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3869

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What are the different ways in which antenna violation can be prevented?

1127

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What is the difference between synchronous and asynchronous reset?

1094

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1257

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Explain the Various steps in Synthesis?

3281

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Explain what is scr (silicon controlled rectifier)?

1064

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2841

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3267

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Explain the working of Insights of an inverter ?

1269

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Are you familiar with the term MESI?

2747

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