Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ?

Answer Posted / adi

Latency is 5 clocks
Throughput is 1 instruction/clock

Is This Answer Correct ?    18 Yes 1 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Explain the Working of a 2-stage OPAMP?

1237


Explain how Verilog is different to normal programming language?

1369


What is the critical path in a SRAM?

3259


How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1248


Basic Stuff related to Perl?

2868


What are the different measures that are required to achieve the design for better yield?

1260


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1350


Explain about 6-T XOR gate?

1366


Mention what are the two types of procedural blocks in Verilog?

1374


Explain CMOS Inverter transfer characteristics?

3964


In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4171


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1503


Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1184


How to improve these parameters? (Cascode topology, use long channel transistors)

2235


6-T XOR gate?

4298