Answer Posted / sailu
Synopsys
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For CMOS logic, give the various techniques you know to minimize power consumption
Explain how Verilog is different to normal programming language?
What's the price in 1K quantity?
If not into production, how far did you follow the design and why did not you see it into production?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What types of CMOS memories have you designed? What were their size? Speed?
what is verilog?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Explain what is scr (silicon controlled rectifier)?
what is multiplexer?
Explain sizing of the inverter?
What is the function of tie-high and tie-low cells?
What is the difference between synchronous and asynchronous reset?
Mention what are the different gates where Boolean logic are applicable?
