Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / santhosh
The Bus Interface Unit (BIU): It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as memory read, I/O read etc. to transfer data between memory and I/O devices.
| Is This Answer Correct ? | 0 Yes | 0 No |
Post New Answer View All Answers
Is the stealth technology is based on the "Reflection coefficient of the material? What are the other factors that affect to optimize this technology
What is a pn junction?
What are the KPI that decides the capacity expansion of SGSN/MME?
why the exchang voltge is in minus polarty i.e -48 instead of +48
Pull the best out of people Put other people above yourself Challenge ideas from another viewpoint Passionate about people Dedication to serving others Pushing people past their limits Never give up Generous of sharing Make other people feel important Thinking outside the box Alternative thinking Complete honesty Wealth of information Easily accessible Work long hours Finding the right answers Working with all ages Dealing with tough situations Making the rounds with other people Compassionate for what people need Diverse in decision Step outside self
What is cache coherence?
What is meant by step-up cyclo-converters?
Explain why vestigial side band is used in tv signal transmission?
interface an 8-pin switch with 8085 microprocessor located at 0AAH and LEDs at port 55H, draw the circuit diagram. Write down a program to read the switches and do the following: > if the parity of the switch is odd, start counting upward until it reaches 0FFH. > if the parity of the switch is even, start counting downwards until it reaches 00H.
types of communication scheme in power plant ?
What are the commonly used filters?
What is meant by commutation?
What is an astable multivibrator?
Plz send previous gate ece question papers with answers of 10 years to my email id .My id is seenu469@gmail.com .Thank u sir
Compare the features of the three transistor configurations.
