Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
Answer Posted / arpan
There are many reasons for which NAND is preferred over NOR
but the most technical reason is LOGICAL EFFORT. So, lets
start with what is logical effort.
1. Logical effort :- It is defined as the ratio of the input
capacitance of the gate to the input capacitance of the
inverter, that can deliver the same output current. In other
terms we can say logical effort indicates how worse a gate
is in producing output current as compared to an inverter,
given each input of the gate has input capacitance
equivalent to an inverter. Suppose for a inverter PMOS width
is 2 and NMOS width is 1. So, here Cin = 3
NAND NOR
Cin = (n+2) Cin = (2n+1)
Cin = 4 Cin = 5
Logical Effort (g) = Cin(NAND)/Cin(Inverter)
g= 4/3 g= 5/3
So, from the above logical effort of NOR is greater than
NAND. So, NAND performs better o/p current compare to NOR.
2. In NAND PMOS is connected in parallel whereas in NOR PMOS
is connected in series, which makes the device operation slow.
Is This Answer Correct ? | 4 Yes | 0 No |
Post New Answer View All Answers
What are the main issues associated with multiprocessor caches and how might you solve them?
What transistor level design tools are you proficient with? What types of designs were they used on?
what is SCR (Silicon Controlled Rectifier)?
Explain how binary number can give a signal or convert into a digital signal?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What happens if we delay the enabling of Clock signal?
Explain the working of Insights of a pass gate ?
Explain Basic Stuff related to Perl?
Explain Cross section of an NMOS transistor?
Write a VLSI program that implements a toll booth controller?
Explain how Verilog is different to normal programming language?
Mention what are the different gates where Boolean logic are applicable?
Are you familiar with the term MESI?
If not into production, how far did you follow the design and why did not you see it into production?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?