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Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
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Answer Posted / arpan
There are many reasons for which NAND is preferred over NOR
but the most technical reason is LOGICAL EFFORT. So, lets
start with what is logical effort.
1. Logical effort :- It is defined as the ratio of the input
capacitance of the gate to the input capacitance of the
inverter, that can deliver the same output current. In other
terms we can say logical effort indicates how worse a gate
is in producing output current as compared to an inverter,
given each input of the gate has input capacitance
equivalent to an inverter. Suppose for a inverter PMOS width
is 2 and NMOS width is 1. So, here Cin = 3
NAND NOR
Cin = (n+2) Cin = (2n+1)
Cin = 4 Cin = 5
Logical Effort (g) = Cin(NAND)/Cin(Inverter)
g= 4/3 g= 5/3
So, from the above logical effort of NOR is greater than
NAND. So, NAND performs better o/p current compare to NOR.
2. In NAND PMOS is connected in parallel whereas in NOR PMOS
is connected in series, which makes the device operation slow.
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