Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

Factors affecting Power Consumption on a chip?

Answer Posted / srujana

Power consumption on a chip can be classified majorly in
to 2 types:
1. Static Power consumption
2. Dynamic Power consumption
Static Power consumption: Leakage power is the major
contributor in static power consumption. The subthreshold
leakage power due to reduced threshold value due to
reduced supply voltages as technology is shrinking is the
major contributor of leakage power.
Dynamic Power consumption:
1.This is due to the increase in frequency of the chip,
which results in high switching rates of the clock
2. Due to increase in the complexity of the chip and the
increase in the instance count of the chip.

Is This Answer Correct ?    16 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

What types of CMOS memories have you designed? What were their size? Speed?

3146


If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1128


Cross section of a PMOS transistor?

4776


What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1348


Write a VLSI program that implements a toll booth controller?

3995


How can you construct both PMOS and NMOS on a single substrate?

4989


what is multiplexer?

1172


How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1211


why is the number of gate inputs to CMOS gates usually limited to four?

1348


Give the cross-sectional diagram of the cmos.

1002


What was your role in the silicon evaluation/product ramp? What tools did you use?

3735


Design an 8 is to 3 encoder using 4 is to encoder?

1338


For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2407


Explain why is the number of gate inputs to cmos gates usually limited to four?

1514


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1302