What r the phenomenon which come into play when the devices
are scaled to the sub-micron lengths?
- 4 Answers
- 6948 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / maroof husain
When divice length scaled down, we acheive high spped
| Is This Answer Correct ? | 1 Yes | 1 No |
Post New Answer View All Answers
How can you construct both PMOS and NMOS on a single substrate?
What are the steps involved in designing an optimal pad ring?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What is the function of chain reordering?
What are the steps required to solve setup and hold violations in vlsi?
What are the different design techniques required to create a layout for digital circuits?
Explain the working of Insights of an inverter ?
what are three regions of operation of MOSFET and how are they used?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Give the cross-sectional diagram of the cmos.
What is the difference between synchronous and asynchronous reset?
Explain Cross section of an NMOS transistor?
What types of CMOS memories have you designed? What were their size? Speed?
What does it mean “the channel is pinched off”?
