Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What is the most complicated/valuable program you written in
C/C++?

Answer Posted / monishaah

number puzzle game

Is This Answer Correct ?    2 Yes 6 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1135


Explain what is scr (silicon controlled rectifier)?

1064


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3869


what is the difference between the TTL chips and CMOS chips?

1133


Design an 8 is to 3 encoder using 4 is to encoder?

1333


Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1204


Draw the stick diagram of a NOR gate. Optimize it

1293


Write a program to explain the comparator?

1156


What types of CMOS memories have you designed? What were their size? Speed?

4662


What types of high speed CMOS circuits have you designed?

2576


Give various factors on which threshold voltage depends.

1306


What are the changes that are provided to meet design power targets?

1122


Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1663


Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3796


Explain what is Verilog?

1113