Interested to Buy Any Domain ? << Click Here >> for more details...
Differences between DRAM and SRAM?
- 14 Answers
- 73249 Views
- Infosys, Intel, University, Wipro, I also Faced
- E-Mail Answers
Answer Posted / anuj gupta
1.SRAM will maintain its data as long as power is provided
to memory chips.it does not require to be rewrite frequently.
2*.the SRAM consists essentially of internal flip flops that
store the binary information
3.SRAM is faster than DRAM
4. SRAM is often used as cache memory due to its speed
1.DRAM is called dynamic because it must constantly be
refreshed we can said that it will lose the data which we
supposed to be storing.
2*.the DRAM stores the information in the form of electric
charges that are applied to capacitors
3.DRAM chips requires only 1 transistor and a capacitor per bit.
| Is This Answer Correct ? | 29 Yes | 8 No |
Post New Answer View All Answers
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
What happens if we delay the enabling of Clock signal?
Explain how logical gates are controlled by Boolean logic?
What are the various regions of operation of mosfet? How are those regions used?
why is the number of gate inputs to CMOS gates usually limited to four?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Why does the present vlsi circuits use mosfets instead of bjts?
What are the different gates where boolean logic are applicable?
Explain the Various steps in Synthesis?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
What are the Advantages and disadvantages of Mealy and Moore?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
what is a sequential circuit?
