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Answer Posted / viji
Foundry(Semiconductor Manufacturers)
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Explain the Charge Sharing problem while sampling data from a Bus?
What are the main issues associated with multiprocessor caches and how might you solve them?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
How does Vbe and Ic change with temperature?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Explain the operation considering a two processor computer system with a cache for each processor.
Draw the stick diagram of a NOR gate. Optimize it
Explain about 6-T XOR gate?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Implement a 2 I/P and gate using Tran gates?
What was your role in the silicon evaluation or product ramp? What tools did you use?
If not into production, how far did you follow the design and why did not you see it into production?
Differences between Array and Booth Multipliers?
How logical gates are controlled by boolean logic?
What is the critical path in a SRAM?
