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whether the mulitasking and multiprocessing are same or
not.
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Answer Posted / jayasuriya
Multitasking implies time sharing, its like a single person
doing different jobs, obviously at different time slices.
Multiprocessing involves some amount of parallelism, if the
hardware supports (eg: dual core, hyper threading etc.)
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This program is in verilog and need help to get it working correctly. This is the code i have so far. Please help. Simple testbench would be great. Thanks\ 'define vend_a_drink {D,dispense,collect} = {IDLE,2'b11}; module drink_machine(nickel_in, dime_in, quarter_in, collect, nickel_out, dime_out, dispense, reset, clk) ; parameter IDLE=0,FIVE=1,TEN=2,TWENTY_FIVE=3, FIFTEEN=4,THIRTY=5,TWENTY=6,OWE_DIME=7; input nickel_in, dime_in, quarter_in, reset, clk; output collect, nickel_out, dime_out, dispense; reg collect, nickel_out, dime_out, dispense; reg [2:0] D, Q; /* state */ // synopsys state_vector Q always @ ( nickel_in or dime_in or quarter_in or reset ) begin nickel_out = 0; dime_out = 0; dispense = 0; collect = 0; if ( reset ) D = IDLE; else begin D = Q; case ( Q ) IDLE: if (nickel_in) D = FIVE; else if (dime_in) D = TEN; else if (quarter_in) D = TWENTY_FIVE; FIVE: if(nickel_in) D = TEN; else if (dime_in) D = FIFTEEN; else if (quarter_in) D = THIRTY; TEN: if (nickel_in) D = FIFTEEN; else if (dime_in) D = TWENTY; else if (quarter_in) 'vend_a_drink; TWENTY_FIVE: if( nickel_in) D = THIRTY; else if (dime_in) 'vend_a_drink; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; dime_out = 1; end FIFTEEN: if (nickel_in) D = TWENTY; else if (dime_in) D = TWENTY_FIVE; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; end THIRTY: if (nickel_in) 'vend_a_drink; else if (dime_in) begin 'vend_a_drink; nickel_out = 1; end else if (quarter_in) begin 'vend_a_drink; dime_out = 1; D = OWE_DIME; end TWENTY: if (nickel_in) D = TWENTY_FIVE; else if (dime_in) D = THIRTY; else if (quarter_in) begin 'vend_a_drink; dime_out = 1; end OWE_DIME: begin dime_out = 1; D = IDLE; end endcase end end always @ (posedge clk ) begin Q = D; end endmodule
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