Answer Posted / indu pillai

Yes SDLC can be maped to STLC with the help of V model.
I have tried to show it
1. Requirement Specifications ----------> Acceptance Test
Acceptance TP Cases

2. Functional design -------------------> System Test Cases
System TP

3. Detailed design ------------------->Integrated Test Cases
Integrated TP

4. Program Specifications--------------->Unit Test Cases
Unit TP

TP refers to Test Plan and not Time Pass :)

So in each of the phases of SDLC , we start planning and
writing Test Cases accordingly,this is how u map SDLC with
STLC.

Hope my answer was fruitful to you

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