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In a cached system, the base addresses of the last few
referenced pages is maintained in registers called the TLB
that aids in faster lookup.
TLB contains those page-table entries that have been most
recently used.
Normally, each virtual memory reference causes 2 physical
memory accesses-- one to fetch appropriate page-table
entry, and one to fetch the desired data. Using TLB in-
between, this is reduced to just one physical memory access
in cases of TLB-hit.
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