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Fortran cannot have value by reference True or False?
Explain the types of operations? Draw the figure for shift and rotate operations?
SYNFOSYS PLACEMENT PAPER 2010 Hi Friends I have attended the recent synfosys test 2010. Here r some questions which i remember. Section – I 1) There are 12 balls weigh similar but one is dissimilar (more/less). How to find the dissimilar ball with minimum no of weighs? 2) There r 7people carrying 7bags. Each bag contains 7cats. Each cat has 7small cats. How many total legs r there? 3) There are 12 balls weigh similar but one is dissimilar (more/less). How to find the dissimilar ball with minimum no of weighs? 4) 5) There r 2 poles each 15 meters high. A cable of length 16 meters is tied between pillars top. For its maximum the cable lies down above 7mts high from the ground. What is the distance between pillars? ------------------------------------------------------------ ------------------------------------------------ Section -II What is the value of 11^5 Some Other quetions ------------------------------------------------------------ ------------------------------------------------ Section - III 16) Serialization and deserialization? 17) Will finally block execute even though there is an exception & return statement are there in catch block? Explain? 18) memory leak? How can we avoid it? 19) virtual destructor? 20) Two program codes for code optimization? ------------------------------------------------------------ ------------------------------------------------ Section – IV Q) Program for finding the alternate digits of the number If number is 35846 then Sum1=3+8+6=17 Sum2=5+4=9 Q) Program for Single linked list? ------------------------------------------------------------ ------------------------------------------------ Section - V Q) What is software engineering? Explain SDLC Q) Explain any two upcoming IT Scenarios? ------------------------------------------------------------ ------------------------------------------------ Regards Gopinath Allanku +91 9885457211
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Can i please VHDL code for D-Latch with clear input ?? (HINT: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs and Outputs: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
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