I m Abdullah Ansari compleated MCA from Jamia Hamdard,i have appeared the test of IBM on 2 august at oxford college of engineering Bangalore.waiting for hr round.. This is the first round for IBM.02/08/08 Paper consists of 4 sections 15 questions from matrices(time very less but no negative marking). 25 questions from series completion section (this section is very easy but negative marking) 15 questions from aptitude(little bit tough time limit 15 minute negative marking) 4th section is from computer science (c,c++,operating system,digital electronics ,basic question..) result came at 3 o'clock.i was selected... In interview they asked questions like 1 they asked about final yr project.. 2 what are dynamic and static memory location? 3 linked list and array difference between them. 4 what is function ? what is difference betwen function and inline function? 5 about structure 6 about binary tree, traversal, call by value. 7 storage class and many more basic questions..
Explain the applications of nmr spectroscopy?
What is pair rdd?
State the difference between a library and a list?
how you can several classes at once?
How to Detect how many jobs are in the print spooler?
What are macros in word?
1)can any body tell the transport request number concept and 2)there are 3 screens in one screen u have uploaded the resume and second screen also u have done the same thing but when u are uploading the resume in third screen u got some error in somewhere else but whatever u have uploaded the resume in 1 and 2 should not
What are the 5 operating system?
Explain different ways of creating a thread. Which one would you prefer and why?
Hi friends, I'm final year mechanical engineering student.Next week i have a campus interview from mando india ltd company.I've prepared aps and reasoning questions well.any one of you guide me to prepare technical questions.kindly give some idea about overall question pattern.
What is the benefit to the data model for using an in-memory platform?
How servo stabilizer works.
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
What is the difference between a port address a logical address and a physical address?