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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1668You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1576What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1348How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1211For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1281Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1485Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1301For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1464Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1307Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1465
Explain the Charge Sharing problem while sampling data from a Bus?
Explain the working of 4-bit Up/down Counter?
How logical gates are controlled by boolean logic?
If not into production, how far did you follow the design and why did not you see it into production?
Basic Stuff related to Perl?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Explain Cross section of a PMOS transistor?
Explain sizing of the inverter?
What transistor level design tools are you proficient with? What types of designs were they used on?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Explain the operation considering a two processor computer system with a cache for each processor.
Describe the various effects of scaling?
How does Vbe and Ic change with temperature?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
