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VLSI Interview Questions
Questions Answers Views Company eMail

Draw a 6-T SRAM Cell and explain the Read and Write operations

Infosys,

817

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

Infosys,

1111

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

Infosys,

1003

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

Infosys,

782

Draw a CMOS Inverter. Explain its transfer characteristics

Infosys,

680

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

Infosys,

752

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

Infosys,

732

For CMOS logic, give the various techniques you know to minimize power consumption

Infosys,

877

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

Infosys,

810

Draw the SRAM Write Circuitry

Infosys,

678

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

Infosys,

872

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

Infosys,

842

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

Infosys,

960

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

Infosys,

805

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Infosys,

899

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Un-Answered Questions { VLSI }

Explain how Verilog is different to normal programming language?

694

Differences between IRSIM and SPICE?

4965

For CMOS logic, give the various techniques you know to minimize power consumption

877

What are the different ways in which antenna violation can be prevented?

680

What is the function of chain reordering?

632




What is the difference between the mealy and moore state machine?

606

Explain the Charge Sharing problem while sampling data from a Bus?

4202

Mention what are three regions of operation of mosfet and how are they used?

602

Explain how binary number can give a signal or convert into a digital signal?

682

How to improve these parameters? (Cascode topology, use long channel transistors)

1723

Explain Cross section of an NMOS transistor?

580

Basic Stuff related to Perl?

2417

What is Noise Margin? Explain the procedure to determine Noise Margin?

1989

What happens if we delay the enabling of Clock signal?

1816

what are three regions of operation of MOSFET and how are they used?

692

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