Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
652Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
912In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
700Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
710Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
737Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
705
why is the number of gate inputs to CMOS gates usually limited to four?
If not into production, how far did you follow the design and why did not you see it into production?
How can you model a SRAM at RTL Level?
What are the Advantages and disadvantages of Mealy and Moore?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Are you familiar with the term snooping?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Design an 8 is to 3 encoder using 4 is to encoder?
What transistor level design tools are you proficient with? What types of designs were they used on?
What does it mean “the channel is pinched off”?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Explain Basic Stuff related to Perl?
How does a Bandgap Voltage reference work?
What is the difference between nmos and pmos technologies?
