Answer / larson

Data Bus, Adress bus and control bus.

Answer / arpit raj

Buses are divided into three subassemblies:

The address bus transports memory addresses which the
processor wants to access in order to read or write data. It
is a unidirectional bus.

The data bus transfers instructions coming from or going to
the processor. It is a bidirectional bus.

The control bus transports orders and synchonisation signals
coming from the control unit and travelling to all other
hardware components. It is a bidirectional bus, as it also
transmits response signals from the hardware.


There are primary buses which are of two types:

There are generally two buses within a computer:

the internal bus (front-side bus, or FSB for short). The
internal bus allows the processor to communicate with the
system's central memory (the RAM).

the expansion bus (input/output bus) allows various
motherboard components (USB, serial, and parallel ports,
cards inserted in PCI connectors, hard drives, CD-ROM and
CD-RW drives, etc.) to communicate with one another.
However, it is mainly used to add new devices using what are
called expansion slots connected to the input/outpur bus.

Answer / ravi

Yes.
1.Memory processor bus= high speed, short length.
2.I/O bus.
3.Backplane bus= General purpose bus ex PCI

Answer / guest

yes
data bus& address bus

Answer / amar

High speed processor bus like AHB where CPU , DMA , Memories
sits

Slow peripheral buses for interfacing periphaerals like APB

What is the difference between cmos and bipolar technologies?

0 Answers  

What was your role in the silicon evaluation/product ramp? What tools did you use?

0 Answers   Intel,

Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

0 Answers  

Explain the Various steps in Synthesis?

0 Answers   Intel,

Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

What are the different measures that are required to achieve the design for better yield?

0 Answers  

What are the different ways in which antenna violation can be prevented?

0 Answers  

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

What is the main function of metastability in vsdl?

0 Answers  

What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,