Answer / amar

this situation basically arises when a signal does clock
domain crossing. to synchronize the clock with the target
domain clock and to avoid metastability issues synchronizers
which are like double clocking are used in designs

Answer / prashant patil

if the input signal is asynchronous with the clock (state
machine clock), then you need to double clock the same
signal to synchronize with the state machine clock.

Answer / prasanna

When signal transfer from one clock domain sequential to
another clock domain sequential logic

Given a circuit and asked to tell the output voltages of that circuit?

1 Answers   Intel, Omega Healthcare,

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For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 Answers  

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

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What is interrupt latency?

3 Answers  

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Draw the SRAM Write Circuitry

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Basic Stuff related to Perl?

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What happens to delay if you increase load capacitance?

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What does it mean “the channel is pinched off”?

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Give the expression for CMOS switching power dissipation?

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Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

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